Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme

This brief presents a time-to-digital converter (TDC) with a three-level conversion scheme based on a dual delay-locked loop (DLL) structure. The linear-feedback-shift-register counter is implemented for measurement range extension, and a differential delay cell is adopted for time resolution improvement. Furthermore, the DLL is applied to improve the stability of themultiphase clock frequency. The test chip is designed and fabricated in a Taiwan SemiconductorManufacturing Company 0.35-mu m CMOS process. With an input reference clock of 40 MHz, the total 15-bit three-level TDC can realize a 3-mu s maximum range and a 476-ps resolution. The differential nonlinearity is less than +/- 0.65 LSB, and the integral nonlinearity is within -1.35 LSB to +1.4 LSB.