Implementation of a High-Precision and Wide-Range Time-to-Digital Converter With Three-Level Conversion Scheme

被引：16

作者：

Wu, Jin ^{[1
]}

Jiang, Qi ^{[2
]}

Song, Ke ^{[2
]}

Zheng, Lixia ^{[1
]}

Sun, Dongchen ^{[2
]}

Sun, Weifeng ^{[2
]}

机构：

[1] Southeast Univ, Wuxi Branch, Wuxi 214000, Peoples R China

[2] Southeast Univ, Inst Integrated Circuit, Nanjing 210018, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2017年 / 64卷 / 02期

基金：

中国国家自然科学基金;

关键词：

Delay-locked loop (DLL); measurement range; time resolution; time-to-digital converter (TDC);

D O I：

10.1109/TCSII.2016.2554818

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a time-to-digital converter (TDC) with a three-level conversion scheme based on a dual delay-locked loop (DLL) structure. The linear-feedback-shift-register counter is implemented for measurement range extension, and a differential delay cell is adopted for time resolution improvement. Furthermore, the DLL is applied to improve the stability of themultiphase clock frequency. The test chip is designed and fabricated in a Taiwan SemiconductorManufacturing Company 0.35-mu m CMOS process. With an input reference clock of 40 MHz, the total 15-bit three-level TDC can realize a 3-mu s maximum range and a 476-ps resolution. The differential nonlinearity is less than +/- 0.65 LSB, and the integral nonlinearity is within -1.35 LSB to +1.4 LSB.

引用

页码：181 / 185

页数：5

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