Sorting devices for the CSC muon trigger system at CMS

The electronics system of the Cathode Strip Chamber (CSC) muon detector at the CMS experiment needs to acquire precise muon position and timing information and generate muon trigger primitives for the Level-1 trigger system. CSC trigger primitives (called Local Charged Tracks, LCT) are formed by anode (ALCT) and cathode (CLCT) cards [1]. ALCT cards are mounted on chambers, while CLCT cards are combined with the Trigger Motherboards (TMB) that perform a time coincidence of ALCT and CLCT. Every combined CLCT/TMB card (one per chamber) transmits two best combined muon tags to the Muon Port Card (MPC) which serves one CSC sector (8 or 9 chambers). The MPC selects the three best muons out of 18 possible and sends them over 100 m of optical cable to the Track Finder (TF) crate residing in the underground counting room In the current electronics layout the TF crate has 12 Sector Processors (SP), each of which receives the optical streams from several MPC. The SP measures the transverse momentum, pseudo-rapidity and azimuthal angle of each muon and sends its data (up to 3 muons each) to the CSC Muon Sorter (MS) that resides in the middle of the TF crate. The MS selects the four best muons out of 36 possible and transmits them to Global Muon Trigger (GMT) crate for further processing. Data sorting is the primary task of two devices in the CSC trigger chain: the MPC ("3 best muons out of 18") and MS ("4 best muons out of 36"). The total data reduction factor is 54. We propose a common approach to implementation of sorting logic and board construction for both the MPC and MS. They will be based on a single chip programmable logic devices that receive data from the previous trigger level, sort it and transmit the sorting result to the next trigger level. Programmable chips will incorporate input and output FIFO buffers that would represent all possible inputs and outputs for testing and debugging purposes. Finally we will use a common sorting scheme [2] for both designs. The MPC and MS functionality as well as the first results of logic simulation and latency estimates are presented.