A Reconfigurable Single-Photon-Counting Integrating Receiver for Optical Communications

被引:92
作者
Fisher, Edward [1 ]
Underwood, Ian [1 ]
Henderson, Robert [1 ]
机构
[1] Univ Edinburgh, Sch Engn, Inst Integrated Micro & Nano Syst, Edinburgh EH9 3JL, Midlothian, Scotland
基金
英国工程与自然科学研究理事会;
关键词
CMOS; IEEE802.15.7; integrated; integrating receiver; interchip; low-light receiver; OEIC; photon counting; single-photon avalanche diode (SPAD); visible light communications (VLCs); AVALANCHE-DIODE; STANDARD CMOS; PHOTODIODES; DETECTOR; TECHNOLOGY;
D O I
10.1109/JSSC.2013.2253222
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A reconfigurable Single-Photon Avalanche Diode integrating receiver in standard 130 nm CMOS is presented for optical links with an array readout bandwidth of 100 MHz. A maximum count rate of 58 G photon/s is observed, with a dynamic range of approximate to 79 dB, a sensitivity of approximate to-31.7 dBm at 100 MHz and a BER of approximate to 1x10(-9). The sensor core draws 89mW at the maximum count rate and obtains a peak SNR of approximate to 157 dB. We investigate the properties of the receiver for optical communications in the visible spectrum, using its added functionality and reconfigurability to experimentally explore non-ideal influences. The all-digital 32 x 32 SPAD array, achieves a minimum dead time of 5.9 ns, and a median dark count rate of 2.5 kHz/SPAD. The internal gain of SPADs and spatio-temporal summation removes the need for analogue amplification. High noise devices can be weighted or removed to optimize the SNR. The power requirements, transient response and received data are explored and limiting factors similar to those of photodiode receivers are observed.
引用
收藏
页码:1638 / 1650
页数:13
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