The impact of gate to drain spacing on hot-carrier degradation in sub-100 nm Ni-Pt salicidation FinFETs

The impact of gate-to-drain (GtD) spacing on hot carrier reliability in sub-100 nm Ni-Pt self-aligned silicided FinFETs has been analyzed experimentally. FinFETs with long GtD spaces exhibit severe drain current degradation (Delta I-DS/I-DS), but variations in threshold voltage (Delta V-TH/V-TH) and subthreshold swing (Delta SS/SS) are nearly the same as with short GtD spaces. When gate length (L-G) is downscaled from 1 mu m to 40 nm, the degradation between long and short GtD spaces increases from 0.4% to 6.5%. The amount of injected hot electrons into salicide-induced defects in the silicon region accounts for the dominant portion of the difference in the current degradation between short and long GtD spaces. The dependence of hot carrier immunity on GtD spacing has been analyzed by both qualitative and quantitative methods. (C) 2015 Elsevier Ltd. All rights reserved.