Circuit Performance Analysis of Negative Capacitance FinFETs

被引:0
作者
Khandelwal, S. [1 ]
Khan, A. I. [1 ]
Duarte, J. P. [1 ]
Sachid, A. B. [1 ]
Salahuddin, S. [1 ]
Hu, C. [1 ]
机构
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
来源
2016 IEEE SYMPOSIUM ON VLSI TECHNOLOGY | 2016年
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中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Circuit-level performance analysis of negative capacitance FinFETs (NC-FinFET) is presented for ultra-low power high performance applications. Circuit simulations are performed by developing a compact model which solves Landau-Khalatnikov (L-K) equations self-consistently with the three-dimensional device electrostatics of the FinFET device. Using an accurate L-g = 30 nm FinFET model, L-K model parameters of ferroelectric (FE) layer are extracted from an experimental NC-FinFET data. With the experimentally calibrated model, we show for the first time that for the same inverter delay as the 14 nm ITRS FinFET, V-dd for NC-FinFET can be lowered from 0.7 V to 0.25 V, reducing energy by similar to 10x. Optimization of the FE layer parameters can further boost the device performance.
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页数:2
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