A 0.5V 12-bit SAR ADC using Adaptive Time-Domain Comparator with Noise Optimization

This paper presents a low voltage and power efficient 12-bit successive-approximation register (SAR) analog-to-digital converter (ADC). The proposed adaptive time-domain (ATD) comparator automatically adjusts its input-referred noise performance according to the intermediate residual input level (Delta V-in) during conversion. Considering the noise requirement of 12-bit SAR ADC, the proposed implementation effectively reduces the comparator power consumption by 50% compared with the conventional approach. The prototyped ADC is fabricated in 90nm CMOS technology with a core area of 0.109mm(2). At 0.5V supply voltage and 150-to-250kS/s sampling rate with a Nyquist input, the implemented ADC achieves a SNDR of 63.8 to 66.3 dB with a corresponding ENOB of 10.3 to 10.71 bits. The resulting figure-of-merit (FoM) are 4.52 to 4.82 fJ/conversion-step.