Area efficient layouts of the Batcher sorting networks

被引:0
作者
Even, S [1 ]
机构
[1] Technion Israel Inst Technol, Dept Comp Sci, IL-32000 Haifa, Israel
[2] Lucent Technol, Bell Labs, Murray Hill, NJ USA
关键词
sorting networks; Batcher; bitonic; odd-even; grid area; VLSI; ATM switch; bounds;
D O I
10.1002/net.10003.abs
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In the early 1980s, the grid area required by the sorting nets of Batcher for input vectors of length N was investigated by Thompson. He showed that the Omega (N-2) area was necessary and sufficient, but the hidden constant factors, both for the lower and upper bounds, were not discussed. In this paper, a lower bound of (N - 1)(2)/2 is proven, for the area required by any sorting network. Upper bounds of 4N(2) and 3N(2) are shown for the bitonic sorter and the odd-even sorter, respectively. In the layouts, which are presented to establish these upper bounds, slanted lines are used and there are no knock-knees. (C) 2001 John Wiley & Sons, Inc.
引用
收藏
页码:199 / 208
页数:10
相关论文
共 15 条