Low Power Pattern Matching Scheme through FSM State Transition for Next Generation NIDS System

The coordinated matching process is a most challenging task in a present NIDS system over the increase in malicious attacks. Many digital systems have been invented to accommodate increased network traffic rate. The overall NIDS efficiency is degraded when the number of intrusions in the database increased. It will lead the demands of concurrent pattern matching scheme in any Field Programmable Gate Array (FPGA) based NIDS system. In this work, a bit based pattern matching algorithm with FSM state transition controller for both parallel processing and assertion based input payload validity check is proposed. Here during the matching process, the Finite State Machine (FSM) state controller will be used in case of early misdetection to optimize overall matching time in case of a longer pattern where the rule is being divided into sub patterns and the successive matches are halted which is done parallel with sub patterns. To avoid synchronization problem over parallel matching process unique controllers are used which is driven with fully integrated page enabled sub groups. The efficiency of FSM state controlled pattern matching process is proved over speed and power metrics. Here in our proposed NIDS system both delay and power are optimized by 5% and 8% accordingly and it is verified using QUARTUS II EDA tool synthesizer.