Optimal placement of modules on partially reconfigurable device for reconfiguration time improvement

被引：3

作者：

Ouni, Bouraoui ^{[1
]}

Mtibaa, Abdellatif ^{[1
]}

机构：

[1] Ecole Natl Ingenieurs Sousse, Fac Sci Monastir, Monstir, Tunisia

来源：

MICROELECTRONICS INTERNATIONAL | 2012年 / 29卷 / 02期

关键词：

Integrated circuits; Programming and algorithm theory; Micro-circuit technology; Multi chip modules;

D O I：

10.1108/13565361211237707

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Purpose - The purpose of this paper is to reduce the reconfiguration time of a field-programmable gate array (FPGA). Design/methodology/approach - The paper focuses on introducing a new temporal placement algorithm which uses a typical mathematical formalism to optimize the reconfiguration time. Findings - Results show that the algorithm decreases considerably the reconfiguration time compared with famous temporal placement algorithms. Originality/value - The paper proposes a new temporal placement algorithm which optimizes reconfiguration time of modules on the device. The studied evaluation cases show that the proposed algorithm provides very significant results in terms reconfiguration time of modules versus other well-known algorithms used in the temporal placement field. The authors uses the eigenvalue of the Laplacian matrix.

引用

页码：101 / 107

页数：7