An input vector monitoring concurrent BIST architecture based on a precomputed test set

Built-In Self-Test (BIST) techniques constitute an effective and practical approach for VLSI circuits testing. BIST schemes are typically classified into two categories: offline and online. Input vector monitoring concurrent BIST schemes are a class of online techniques that circumvent the problems appearing separately in online and in offline BIST in a very effective way. The utilization of input vector monitoring concurrent BIST techniques provides the capability to perform testing at different stages, manufacturing, periodic offline ( in special test mode), and concurrent online ( in normal mode of operation). The input vector monitoring concurrent BIST schemes proposed so far have targeted either exhaustive or pseudorandom testing separately. In this paper, a novel input vector monitoring concurrent BIST scheme based on a precomputed test set is presented. The proposed scheme can perform both concurrent online and offline testing; therefore, it can be equally well utilized for manufacturing and concurrent online testing in the field. The applicability of the scheme is validated with respect to the hardware overhead and the time required for completion of the test in benchmark circuits. To the best of our knowledge, the proposed scheme is the first to be presented in the open literature based on a precomputed test set that can perform both concurrent online and offline testing.