Prototype Design of Hierarchical Cluster Multiprocessor on Platform FPGA

The MPSoC(Multi-Processor System on Chip) is a promising solution for the coming complex computer and embedded systems. And the the NoC(Network on Chip) architecture has been proposed as an effective interconnection on chip and been used in many designs of high performance embedded systems. But the NoCs and MPSoC bring more challenges on parallel programming and synthesis for applications design. This paper proposes a new hierarchical cluster multiprocessor architecture, which adopts NoC interconnection and hierarchical clusters architecture. And this design has been implemented as a prototype on FPGA. The performances of the prototype is evaluated by a parallel JPEG decoder, and the approach can improve by 143.2%.