Impact of Radiation on the Operation and Reliability of Deep Submicron CMOS Technologies

被引：2

作者：

Claeys, C. ^{[1
,2
]}

Put, S. ^{[1
,2
,3
]}

Griffoni, A. ^{[1
]}

Cester, A. ^{[4
]}

Gerardin, S. ^{[4
,5
]}

Meneghesso, G. ^{[4
]}

Paccagnella, A. ^{[4
,5
]}

Simoen, E. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Dept EE, B-3001 Leuven, Belgium

[3] CEN SCK, Belgian Nucl Res Ctr, B-2400 Mol, Belgium

[4] Univ Padua, Dipartimento Ingn Informazione, I-35131 Padua, Italy

[5] Ist Nazl Fis Nucl, I-35131 Padua, Italy

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010) | 2010年 / 27卷 / 01期

关键词：

THIN GATE OXIDES; HEAVY-ION STRIKES; ELECTRICAL CHARACTERIZATION; SOI MOSFETS; WEAR-OUT; BREAKDOWN; DEGRADATION; IRRADIATION; INTERFACE; GROWTH;

D O I：

10.1149/1.3360593

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

CMOS scaling has a beneficial impact on the radiation hardness of the technologies and often only requires a further optimization of either the Shallow Trench Isolation (STI) or the Buried Oxide (BOX) in case of a SOI technology. From a reliability viewpoint, heavy-ion induced ionization damage in the gate dielectric may lead to Radiation-Induced Leakage Current (RILC), Radiation-induced Soft Breakdown (RSB), Single Event Gate Rupture (SEGR) or the creation of latent damage. This paper discusses the present knowledge of the radiation impact on the operation and the reliability of deep submicron CMOS technologies.

引用

页码：39 / 46

页数：8

共 50 条

[31] Ionizing radiation effects on CMOS imagers manufactured in deep submicron process
Goiffon, Vincent
Magnan, Pierre
Bernard, Frederic
Rolland, Guy
Saint-Pe, Olivier
Huger, Nicolas
Corbiere, Franck
SENSORS, CAMERAS, AND SYSTEMS FOR INDUSTRIAL/SCIENTIFIC APPLICATIONS IX, 2008, 6816
[32] A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies
Schmitz, A. L.
Tielert, R. L.
ADVANCES IN RADIO SCIENCE, 2005, 3 : 355 - 358
[33] Linear Analysis of Phase Noise in LC oscillators in Deep Submicron CMOS Technologies
Chicco, Francesco
Capoccia, Raffaele
Pezzotta, Alessandro
Enz, Christian
2017 INTERNATIONAL CONFERENCE ON NOISE AND FLUCTUATIONS (ICNF), 2017,
[34] An evaluation of deep-submicron CMOS design optimized for operation at 77 K
Foty, Daniel
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2006, 49 (02) : 97 - 105
[35] An evaluation of deep-submicron CMOS design optimized for operation at 77 K
Daniel Foty
Analog Integrated Circuits and Signal Processing, 2006, 49 : 97 - 105
[36] Design methodology of deep submicron CMOS devices for 1V operation
Oyamatsu, H
Kinugawa, M
Kakumu, M
IEICE TRANSACTIONS ON ELECTRONICS, 1996, E79C (12) : 1720 - 1725
[37] Performance and reliability aspects of FOND: A new deep submicron CMOS device concept
Bellens, R
VandenBosch, G
Habas, P
Mieville, JP
Badenes, G
Clerix, A
Groeseneken, G
Deferm, L
Maes, HE
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1996, 43 (09) : 1407 - 1415
[38] A spice-like reliability model for deep-submicron CMOS technology
Cui, Z
Liou, JJ
SOLID-STATE ELECTRONICS, 2005, 49 (10) : 1702 - 1707
[39] Impact analysis of deep-submicron CMOS technologies on the voltage and temperature independence of a time-domain sensor interface
Valentijn De Smedt
Georges Gielen
Wim Dehaene
Analog Integrated Circuits and Signal Processing, 2015, 82 : 285 - 296
[40] Impact analysis of deep-submicron CMOS technologies on the voltage and temperature independence of a time-domain sensor interface
De Smedt, Valentijn
Gielen, Georges
Dehaene, Wim
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2015, 82 (01) : 285 - 296

← 1 2 3 4 5 →