Impact of Radiation on the Operation and Reliability of Deep Submicron CMOS Technologies

被引：2

作者：

Claeys, C. ^{[1
,2
]}

Put, S. ^{[1
,2
,3
]}

Griffoni, A. ^{[1
]}

Cester, A. ^{[4
]}

Gerardin, S. ^{[4
,5
]}

Meneghesso, G. ^{[4
]}

Paccagnella, A. ^{[4
,5
]}

Simoen, E. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Dept EE, B-3001 Leuven, Belgium

[3] CEN SCK, Belgian Nucl Res Ctr, B-2400 Mol, Belgium

[4] Univ Padua, Dipartimento Ingn Informazione, I-35131 Padua, Italy

[5] Ist Nazl Fis Nucl, I-35131 Padua, Italy

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010) | 2010年 / 27卷 / 01期

关键词：

THIN GATE OXIDES; HEAVY-ION STRIKES; ELECTRICAL CHARACTERIZATION; SOI MOSFETS; WEAR-OUT; BREAKDOWN; DEGRADATION; IRRADIATION; INTERFACE; GROWTH;

D O I：

10.1149/1.3360593

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

CMOS scaling has a beneficial impact on the radiation hardness of the technologies and often only requires a further optimization of either the Shallow Trench Isolation (STI) or the Buried Oxide (BOX) in case of a SOI technology. From a reliability viewpoint, heavy-ion induced ionization damage in the gate dielectric may lead to Radiation-Induced Leakage Current (RILC), Radiation-induced Soft Breakdown (RSB), Single Event Gate Rupture (SEGR) or the creation of latent damage. This paper discusses the present knowledge of the radiation impact on the operation and the reliability of deep submicron CMOS technologies.

引用

页码：39 / 46

页数：8

共 50 条

[11] Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies
Rossi, P
Svelto, F
Mazzanti, A
Andreani, P
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2005, 42 (01) : 31 - 36
[12] Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies
Paolo Rossi
Francesco Svelto
Andrea Mazzanti
Pietro Andreani
Analog Integrated Circuits and Signal Processing, 2004, 42 (1) : 31 - 36
[13] Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
Nardi, A
Neviani, A
Zanoni, E
Quarantelli, M
Guardiani, C
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, 1999, 12 (04) : 396 - 402
[14] Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies
IEEE
不详
不详
不详
IEEE Trans Semicond Manuf, 4 (396-402):
[15] Reduced Impact of Induced Gate Noise on Inductively Degenerated LNAs in Deep Submicron CMOS Technologies
Paolo Rossi
Francesco Svelto
Andrea Mazzanti
Pietro Andreani
Analog Integrated Circuits and Signal Processing, 2005, 42 : 31 - 36
[16] Deep submicron CMOS integrated circuit reliability simulation with SPICE
Li, XJ
Huang, B
Qin, J
Zhang, X
Talmor, M
Gur, Z
Bernstein, JB
6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2005, : 382 - 389
[17] Analog Signal Processing in Deep Submicron CMOS Technologies using Inverters
Raghunandan, K. R.
Sun, Nan
Viswanathan, T. R.
2014 IEEE 57TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2014, : 394 - 397
[18] A novel scalable spiking pixel architecture for deep submicron CMOS technologies
Boussaid, Farid
Chen Shoushun
Bermak, Amine
IEEE DTIS: 2006 INTERNATIONAL CONFERENCE ON DESIGN & TEST OF INTEGRATED SYSTEMS IN NANOSCALE TECHNOLOGY, PROCEEDINGS, 2006, : 131 - 135
[19] A new highly linear CMOS mixer suitable for deep submicron technologies
Salem, RF
Galal, SH
Tawfik, MS
Ragaie, HF
ICES 2002: 9TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-111, CONFERENCE PROCEEDINGS, 2002, : 81 - 84
[20] Impact of nitrogen profile in gate nitrided-oxide on deep-submicron CMOS performance and reliability
Takasaki, K
Irino, K
Aoyama, T
Momiyama, Y
Nakanishi, T
Tamura, Y
Ito, T
FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 2003, 39 (01): : 40 - 51

← 1 2 3 4 5 →