Impact of Radiation on the Operation and Reliability of Deep Submicron CMOS Technologies

被引：2

作者：

Claeys, C. ^{[1
,2
]}

Put, S. ^{[1
,2
,3
]}

Griffoni, A. ^{[1
]}

Cester, A. ^{[4
]}

Gerardin, S. ^{[4
,5
]}

Meneghesso, G. ^{[4
]}

Paccagnella, A. ^{[4
,5
]}

Simoen, E. ^{[1
]}

机构：

[1] IMEC, Kapeldreef 75, B-3001 Louvain, Belgium

[2] Katholieke Univ Leuven, Dept EE, B-3001 Leuven, Belgium

[3] CEN SCK, Belgian Nucl Res Ctr, B-2400 Mol, Belgium

[4] Univ Padua, Dipartimento Ingn Informazione, I-35131 Padua, Italy

[5] Ist Nazl Fis Nucl, I-35131 Padua, Italy

来源：

CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2010 (CSTIC 2010) | 2010年 / 27卷 / 01期

关键词：

THIN GATE OXIDES; HEAVY-ION STRIKES; ELECTRICAL CHARACTERIZATION; SOI MOSFETS; WEAR-OUT; BREAKDOWN; DEGRADATION; IRRADIATION; INTERFACE; GROWTH;

D O I：

10.1149/1.3360593

中图分类号：

O646 [电化学、电解、磁化学];

学科分类号：

081704 ;

摘要：

CMOS scaling has a beneficial impact on the radiation hardness of the technologies and often only requires a further optimization of either the Shallow Trench Isolation (STI) or the Buried Oxide (BOX) in case of a SOI technology. From a reliability viewpoint, heavy-ion induced ionization damage in the gate dielectric may lead to Radiation-Induced Leakage Current (RILC), Radiation-induced Soft Breakdown (RSB), Single Event Gate Rupture (SEGR) or the creation of latent damage. This paper discusses the present knowledge of the radiation impact on the operation and the reliability of deep submicron CMOS technologies.

引用

页码：39 / 46

页数：8

共 50 条

[1] Radiation hardening of ASICs in deep submicron CMOS technologies
Szczygiel, R
PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS III, 2005, 5775 : 103 - 110
[2] Deep submicron CMOS technologies for the LHC experiments
Jarron, P
Anelli, G
Calin, T
Cosculluela, J
Campbell, B
Delmastro, M
Faccio, F
Giraldo, A
Heijne, E
Kloukinas, K
Letheren, M
Nicolaidis, M
Moreira, P
Paccagnella, A
Marchioro, A
Snoeys, W
Velazco, R
NUCLEAR PHYSICS B-PROCEEDINGS SUPPLEMENTS, 1999, 78 : 625 - 634
[3] Deep-submicron CMOS technologies for low-power and high-performance operation
Deura, Manabu
Nara, Yasuo
Yamazaki, Tatsuya
Gotoh, Kenichi
Ohtake, Fumio
Kurata, Hajime
Sugii, Toshihiro
Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), 1996, 79 (11): : 1 - 9
[4] Deep-submicron CMOS technologies for low-power and high-performance operation
Deura, M
Nara, Y
Yamazaki, T
Gotoh, K
Ohtake, F
Kurata, H
Sugii, T
ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS, 1996, 79 (11): : 1 - 9
[5] Integration of NiSi SALICIDE for deep submicron CMOS technologies
Lin, XW
Ibrahim, N
Topete, L
Pramanik, D
ADVANCED INTERCONNECTS AND CONTACT MATERIALS AND PROCESSES FOR FUTURE INTEGRATED CIRCUITS, 1998, 514 : 179 - 184
[6] The effect of substrate radiation-induced defects on the operation of deep submicron silicon technologies
Simoen, E
Claeys, C
Poyai, A
CRYSTALLINE DEFECTS AND CONTAMINATION: THEIR IMPACT AND CONTROL IN DEVICE MANUFACTURING III - DECON 2001, 2001, 2001 (29): : 75 - 92
[7] RF-distortion in deep-submicron CMOS technologies
van Langevelde, R
Tiemeijer, LF
Havens, RJ
Knitel, MJ
Roes, RFM
Woerlee, PH
Klaassen, DBM
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 807 - 810
[8] ESD production for deep submicron triple well CMOS technologies
Nikolaidis, T
Papadas, C
ELECTRONICS LETTERS, 1999, 35 (23) : 2025 - 2027
[9] High-performance, deep-submicron CMOS technologies
Sugii, T
Deura, M
Nara, Y
FUJITSU SCIENTIFIC & TECHNICAL JOURNAL, 1996, 32 (01): : 85 - 93
[10] A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
Estrada, A
Jiménez, CJ
Valencia, M
VLSI Circuits and Systems II, Pts 1 and 2, 2005, 5837 : 902 - 912

← 1 2 3 4 5 →