Hardware Design of Spatial Mapper for 1.73Gbps Multi-User MIMO System of IEEE802.11ac

被引：0

作者：

Setiawan, Hendra ^{[1
]}

Lanante, Leonardo, Jr. ^{[2
]}

Kurosaki, Masayuki ^{[2
]}

Ochi, Hiroshi ^{[2
]}

机构：

[1] Univ Islam Indonesia, Dept Elect Engn, Yogyakarta, Indonesia

[2] Kyushu Inst Technol, Dept Comp Sci & Elect, Fukuoka, Japan

来源：

PROCEEDINGS OF 2013 3RD INTERNATIONAL CONFERENCE ON INSTRUMENTATION, COMMUNICATIONS, INFORMATION TECHNOLOGY, AND BIOMEDICAL ENGINEERING (ICICI-BME) | 2013年

关键词：

Beamforming; spatial mapper; WLAN; multi-user MIMO; IEEE; 802.11ac;

D O I：

暂无

中图分类号：

R318 [生物医学工程];

学科分类号：

0831 ;

摘要：

This paper presents a spatial mapper hardware design using model based RTL provided by Synphony HLS. It is a part of a transmitter system based on IEEE 802.11ac. The speed target is 160MHz in the FPGA Alter a Stratix IV EP4SE820H35C3. For spatial mapper, this speed can be achieved by two stages pipelining. The first pipeline puts inside of the complex multiplier, while the other is after the complex multiplier processing. The compilation result shows that the spatial mapper design can reach up to 203.7MHz and requires 1658 combinational circuits, 2113 ALMs, 3216 registers.

引用

页码：111 / 114

页数：4