Performance Analysis of DA Based Adaptive FIR Filter Using FPGA

被引：0

作者：

Singh, Harpreet ^{[1
]}

Singh, Gurinder ^{[1
]}

Singh, Tarandip ^{[1
]}

机构：

[1] Sri Guru Granth Sahib World Univ, Dept Elect Engn, Fatehgarh Sahib 140406, India

来源：

2014 Annual IEEE India Conference (INDICON) | 2014年

关键词：

Distributed Arithmetic; Least Mean Square; Field Programmable Gate Array; Digital Signal Processing; IMPLEMENTATION;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper, the performance is analyzed based on operating speed, area and memory requirement for the least mean square (LMS) adaptive finite impulse response (FIR) filter using distributed arithmetic (DA). DA technique performs the convolution operation by replacing multipliers with look up tables that result in low resource utilization and high throughput. The throughput and resource utilization factors are related with the number of taps in the DA base unit and these DA base units are required to reduce the memory size and to provide fast updating of memory contents. In this paper, we also analyzed the effect of the number of taps in DA base unit on the memory usage and operating speed of the adaptive FIR filter design.

引用

页数：4

共 7 条

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