Power-Efficient Calibration and Reconfiguration for Optical Network-on-Chip

Recent advances in nanophotonic fabrication have made the optical network-on-chip an attractive interconnect option for next-generation multi-/many-core systems, providing high bandwidth and power efficiency. Both post-fabrication and runtime calibration of the optical components (ring resonators) are essential to building a robust optical communication system, as they are highly sensitive to process and thermal variation. Existing tuning methods based on bias voltage and temperature adjustment require excessive power to fully compensate for these variations. In this work, we propose a set of complementary techniques to address this challenge and significantly reduce the tuning power consumption: 1) a subchannel remapping scheme to decrease the required tuning from the free spectral range to less than one channel (typically less than 1 nm); 2) a transceiver-based network topology capable of building and tuning far fewer rings while maintaining the same system throughput. Our results show that the proposed methods can together reduce the tuning power by as much as 99.85%.