3D Stacking of High-Performance Processors

被引：0

作者：

Emma, Philip ^{[1
]}

Buyuktosunoglu, Alper ^{[1
]}

Healy, Michael ^{[1
]}

Kailas, Krishnan ^{[1
]}

Puente, Valentin ^{[1
]}

Yu, Roy ^{[1
]}

Hartstein, Allan ^{[1
]}

Bose, Pradip ^{[1
]}

Moreno, Jaime ^{[1
]}

机构：

[1] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

2014 20TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA-20) | 2014年

关键词：

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In most 3D work to date, people have looked at two situations: 1) a case in which power density is not a problem, and the parts of a processor and/or entire processors can be stacked atop each other, and 2) a case in which power density is limited, and storage is stacked atop processors. In this paper, we consider the case in which power density is a limitation, yet we stack processors atop processors. We also will discuss some of the physical limitations today that render many of the good ideas presented in other work impractical, and what would be required in the technology to make them feasible. In the high-performance regime, circuits are not designed to be "power efficient;" they're designed to be fast. In power-efficient design, the speed and power of a processor should be nearly proportional. In the high-performance regime, the frequency is (ever progressingly) sublinear in power. Thus, when the power density is constrained - as it is in high-performance machines, there may be opportunities to selectively exploit parallelism in workloads by running processor-on-processor systems at the same power, yet at much greater than half speed.

引用

页码：500 / 511

页数：12

共 10 条

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