A low-swing differential interface circuit for high-speed on-chip asynchronous interconnection

被引：0

作者：

Yang, HZ ^{[1
]}

Qiao, F ^{[1
]}

Huang, G ^{[1
]}

Wang, H ^{[1
]}

机构：

[1] Tsing Hua Univ, Dept Elect Engn, Beijing 100084, Peoples R China

来源：

2005 6th International Conference on ASIC Proceedings, Books 1 and 2 | 2005年

关键词：

low power; low-swing interface circuit; driver-array;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel low-swing interface circuit for asynchronous interconnection is proposed in this paper. It takes a level-triggered differential latch to recover digital signal with ultra low-swing voltage less than 50mV, and the driver part of the interface circuit is optimized for low power using the method of Driver-Array [1] The proposed circuit consumes less power than previously reported designs and can work up to 500MHz, which is simulated and fabricated with SMIC 0.18-mu m 1.8-V digital CMOS technology.

引用

页码：86 / 89

页数：4

共 6 条

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[2]

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[4]

NAVID F, 1995, IEEE J SOLID-ST CIRC, V30, P93

[5]

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[6] Low-swing on-chip signaling techniques: Effectiveness and robustness [J].

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2000, 8 (03) :264-272

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