Vertical Nanowire Heterojunction Devices Based on a Clean Si/Ge Interface

Different vertical nanowire heterojunction devices were fabricated and tested based on vertical Ge nanowires grown epitaxially at low temperatures on (111) Si substrates with a sharp and clean Si/Ge interface. The nearly ideal Si/Ge heterojuctions with controlled and abrupt doping profiles were verified through material analysis and electrical characterizations. In the nSi/pGe heterojunction diode, an ideality factor of 1.16, subpicoampere reverse saturation current, and rectifying ratio of 10(6) were obtained, while the n+Si/p+Ge structure leads to Esaki tunnel diodes with a high peak tunneling current of 4.57 kA/cm(2) and negative differential resistance at room temperature. The large valence band discontinuity between the Ge and Si in the nanowire heterojunctions was further verified in the p+Si/pGe structure, which shows a rectifying behavior instead of an Ohmic contact and raises an important issue in making Ohmic contacts to heterogeneously integrated materials. A raised Si/Ge structure was further developed using a self-aligned etch process, allowing greater freedom in device design for applications such as the tunneling field-effect transistor (TFET). All measurement data can be well-explained and fitted with theoretical models with known bulk properties, suggesting that the Si/Ge nanowire system offers a very clean heterojunction interface with low defect density, and holds great potential as a platform for future high-density and high-performance electronics.