Measurement and simulation of stacked die thermal resistances

被引：7

作者：

Joiner, Bennett ^{[1
]}

Montes de Oca, Jose ^{[2
]}

Neelakantan, Srirarn ^{[1
]}

机构：

[1] Freescale Semicond Inc, Austin, TX 78735 USA

[2] Wright State Univ, Dayton, OH USA

来源：

TWENTY SECOND ANNUAL IEEE SEMICONDUCTOR THERMAL MEASUREMENT AND MANAGEMENT SYMPOSIUM, PROCEEDINGS 2006 | 2006年

关键词：

Theta-JA; thermal; integrated circuit; package; stacked; multi-chip; PBGA; superposition;

D O I：

10.1109/STHERM.2006.1625230

中图分类号：

O414.1 [热力学];

学科分类号：

摘要：

Packages with multiple die provide additional challenges when documenting their thermal performance. To explore the thermal performance of multi-chip packages, stacked die configurations were chosen with the die stacked upon each other. A plastic ball grid array package (PBGA) was thermally tested with three die configurations. The thermal performance of the package was determined using the JEDEC 51 specifications. The package was also simulated using a finite element simulation to better illustrate the package performance. In addition, the validity of the superposition technique was evaluated in the determination of junction temperatures with change in power of the various die.

引用

页码：210 / +

页数：2

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