Improved lifetime of poly-Si TFTs with a self-aligned gate-overlapped LDD structure

被引:14
作者
Mishima, Y [1 ]
Ebiko, Y [1 ]
机构
[1] Fujitsu Labs Ltd, Atsugi, Kanagawa 2430197, Japan
关键词
gate-over lapped lightly doped drain; H-2 ion doping; lifetime; poly-Si TFT;
D O I
10.1109/TED.2002.1003716
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H-2 ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of nonlightly doped drain (non-LDD) and lightly doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.
引用
收藏
页码:981 / 985
页数:5
相关论文
共 9 条
[1]  
EBIKO Y, 2001, P AS DISPL IDW01 KOB, P379
[2]   A NEW SELF-CONSISTENT MODELING APPROACH TO INVESTIGATING MOSFET DEGRADATION [J].
HANSCH, W ;
VONSCHWERIN, A ;
HOFMANN, F .
IEEE ELECTRON DEVICE LETTERS, 1990, 11 (09) :362-364
[3]   A novel self-aligned gate-overlapped LDD poly-Si TFT with high reliability and performance [J].
Hatano, M ;
Akimoto, H ;
Sakai, T .
INTERNATIONAL ELECTRON DEVICES MEETING - 1997, TECHNICAL DIGEST, 1997, :523-526
[4]   NON-MASS-SEPARATED ION SHOWER DOPING OF POLYCRYSTALLINE SILICON [J].
MISHIMA, Y ;
TAKEI, M .
JOURNAL OF APPLIED PHYSICS, 1994, 75 (10) :4933-4938
[5]   High-performance CMOS circuits fabricated by excimer-laser-annealed poly-Si TFTs on glass substrates [J].
Mishima, Y ;
Yoshino, K ;
Takeuchi, F ;
Ohgata, K ;
Takei, M ;
Sasaki, N .
IEEE ELECTRON DEVICE LETTERS, 2001, 22 (02) :89-91
[6]   A new dopant activation technique for poly-Si TFTs with a self-aligned gate-overlapped LDD structure [J].
Ohgata, K ;
Mishima, Y ;
Sasaki, N .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :205-208
[7]   Numerical analysis of the electrical characteristics of gate overlapped lightly doped drain polysilicon thin film transistors [J].
Pecora, A ;
Massussi, F ;
Mariucci, L ;
Fortunato, G ;
Ayres, JR ;
Brotherton, SD .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS, 1999, 38 (6A) :3475-3481
[8]   AN EMPIRICAL-MODEL FOR DEVICE DEGRADATION DUE TO HOT-CARRIER INJECTION [J].
TAKEDA, E ;
SUZUKI, N .
IEEE ELECTRON DEVICE LETTERS, 1983, 4 (04) :111-113
[9]  
YOUNG ND, 1999, IDW 99, P219