共 50 条
- [41] Sidewall spacer layer engineering for improvement of analog/RF performance of nanoscale double-gate junctionless transistors [J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (07): : 2847 - 2857
- [42] Surface potential calculation and drain current model for junctionless double-gate polysilicon TFTs [J]. AIP ADVANCES, 2014, 4 (08):
- [46] Effects of Hafnium Oxide on Short Channel Effects and DC Analysis for Double Gate Junctionless Transistors [J]. Transactions on Electrical and Electronic Materials, 2022, 23 : 430 - 440