Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

被引：36

作者：

Cerdeira, A. ^{[1
]}

Estrada, M. ^{[1
]}

Iniguez, B. ^{[2
]}

Trevisoli, R. D. ^{[3
]}

Doria, R. T. ^{[3
]}

de Souza, M. ^{[3
]}

Pavanello, M. A. ^{[3
]}

机构：

[1] CINVESTAV IPN, Dept Ingn Elect, Secc Elect Estado Solido, Mexico City 07360, DF, Mexico

[2] Univ Rovira & Virgili, Dept Engn Elect Elect & Automat, E-43007 Tarragona, Spain

[3] Ctr Univ FEI, Dept Elect Engn, BR-09850901 Sao Bernardo Do Campo, Brazil

来源：

SOLID-STATE ELECTRONICS | 2013年 / 85卷

基金：

巴西圣保罗研究基金会;

关键词：

JLT; Junctionless transistor; Double-Gate Junctionless Transistor model; Accumulation JLT; Depletion JLT; COMPACT MODEL; MOSFETS;

D O I：

10.1016/j.sse.2013.03.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 x 10(18) and 1 x 10(19) cm(-3), as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to V-d = 0 V. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：59 / 63

页数：5

共 50 条

[21] A unified carrier-based model for symmetric double-gate and surrounding-gate MOS transistors
He, J.
Bian, W.
Tao, Y.
Liu, F.
Zhang, X.
Wu, W.
Wang, T.
Chan, M.
MIXDES 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS:, 2007, : 63 - +
[22] A Compact Model of Quantum Electron Density at the Subthreshold Region for Double-Gate Junctionless Transistors
Duarte, Juan Pablo
Kim, Moon-Seok
Choi, Sung-Jin
Choi, Yang-Kyu
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (04) : 1008 - 1012
[23] Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric
Jiang, Chunsheng
Liang, Renrong
Wang, Jing
Xu, Jun
SOLID-STATE ELECTRONICS, 2016, 126 : 130 - 135
[24] Trans-Capacitance Modeling in Junctionless Symmetric Double-Gate MOSFETs
Jazaeri, Farzan
Barbut, Lucian
Sallese, Jean-Michel
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2013, 60 (12) : 4034 - 4040
[25] A Nonpiecewise Model for Long-Channel Junctionless Cylindrical Nanowire FETs
Duarte, Juan P.
Choi, Sung-Jin
Moon, Dong-Il
Choi, Yang-Kyu
IEEE ELECTRON DEVICE LETTERS, 2012, 33 (02) : 155 - 157
[26] Physically Based Evaluation of Electron Mobility in Ultrathin-Body Double-Gate Junctionless Transistors
Wei, Kangliang
Zeng, Lang
Wang, Juncheng
Du, Gang
Liu, Xiaoyan
IEEE ELECTRON DEVICE LETTERS, 2014, 35 (08) : 817 - 819
[27] Threshold-voltage variability analysis and modeling for junctionless double-gate transistors
Chen, Chun-Yu
Lin, Jyi-Tsong
Chiang, Meng-Hsueh
MICROELECTRONICS RELIABILITY, 2017, 74 : 22 - 26
[28] A Generalized Threshold Voltage Model of Tied and Untied Double-Gate Junctionless FETs for a Symmetric and Asymmetric Structure
Hur, Jae
Choi, Ji-Min
Woo, Jong-Ho
Jang, Hyunjae
Choi, Yang-Kyu
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (09) : 2710 - 2716
[29] A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structures
Jin, Xiaoshi
Liu, Xi
Wu, Meile
Chuai, Rongyan
Lee, Jung-Hee
Lee, Jong-Ho
SOLID-STATE ELECTRONICS, 2013, 79 : 206 - 209
[30] Analytic carrier-based charge and capacitance model for long-channel undoped surrounding-gate MOSFETs
He, Jin
Bian, Wei
Tao, Yadong
Yang, Shengqi
Tang, Xu
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (06) : 1478 - 1485

← 1 2 3 4 5 →