Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

被引：36

作者：

Cerdeira, A. ^{[1
]}

Estrada, M. ^{[1
]}

Iniguez, B. ^{[2
]}

Trevisoli, R. D. ^{[3
]}

Doria, R. T. ^{[3
]}

de Souza, M. ^{[3
]}

Pavanello, M. A. ^{[3
]}

机构：

[1] CINVESTAV IPN, Dept Ingn Elect, Secc Elect Estado Solido, Mexico City 07360, DF, Mexico

[2] Univ Rovira & Virgili, Dept Engn Elect Elect & Automat, E-43007 Tarragona, Spain

[3] Ctr Univ FEI, Dept Elect Engn, BR-09850901 Sao Bernardo Do Campo, Brazil

来源：

SOLID-STATE ELECTRONICS | 2013年 / 85卷

基金：

巴西圣保罗研究基金会;

关键词：

JLT; Junctionless transistor; Double-Gate Junctionless Transistor model; Accumulation JLT; Depletion JLT; COMPACT MODEL; MOSFETS;

D O I：

10.1016/j.sse.2013.03.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 x 10(18) and 1 x 10(19) cm(-3), as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to V-d = 0 V. (C) 2013 Elsevier Ltd. All rights reserved.

引用

页码：59 / 63

页数：5

共 50 条

[1] Compact core model for Symmetric Double-Gate Junctionless Transistors
Cerdeira, A.
Avila, F.
Iniguez, B.
de Souza, M.
Pavanello, M. A.
Estrada, M.
SOLID-STATE ELECTRONICS, 2014, 94 : 91 - 97
[2] Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs-Part I: Drain Current and Transconductances
Makris, Nikolaos
Jazaeri, Farzan
Sallese, Jean-Michel
Sharma, Rupendra Kumar
Bucher, Matthias
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (07) : 2744 - 2750
[3] Compact model for short-channel symmetric double-gate junctionless transistors
Avila-Herrera, F.
Cerdeira, A.
Paz, B. C.
Estrada, M.
Iniguez, B.
Pavanello, M. A.
SOLID-STATE ELECTRONICS, 2015, 111 : 196 - 203
[4] Charge-Based Modeling of Long-Channel Symmetric Double-Gate Junction FETs-Part II: Total Charges and Transcapacitances
Makris, Nikolaos
Jazaeri, Farzan
Sallese, Jean-Michel
Bucher, Matthias
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (07) : 2751 - 2756
[5] Charge-based model for symmetric double-gate MOSFETs with inclusion of channel doping effect
Zhang, Lining
Zhang, Jian
Song, Yan
Lin, Xinnan
He, Jin
Chan, Mansun
MICROELECTRONICS RELIABILITY, 2010, 50 (08) : 1062 - 1070
[6] Generalized Charge-Based Model of Double-Gate Junctionless FETs, Including Inversion
Jazaeri, Farzan
Barbut, Lucian
Sallese, Jean-Michel
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2014, 61 (10) : 3553 - 3557
[7] A simple compact model for long-channel junctionless Double Gate MOSFETs
Lime, Francois
Santana, Ernesto
Iniguez, Benjamin
SOLID-STATE ELECTRONICS, 2013, 80 : 28 - 32
[8] Negative Capacitance Double-Gate Junctionless FETs: A Charge-Based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Rassekh, Amin
Sallese, Jean-Michel
Jazaeri, Farzan
Fathipour, Morteza
Ionescu, Adrian M.
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2020, 8 : 939 - 947
[9] Empirical Model for Nonuniformly Doped Symmetric Double-Gate Junctionless Transistor
Kumari, Vandana
Kumar, Ayush
Saxena, Manoj
Gupta, Mridula
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (01) : 314 - 321
[10] Charge-based compact analytical model for triple-gate junctionless nanowire transistors
Avila-Herrera, F.
Paz, B. C.
Cerdeira, A.
Estrada, M.
Pavanello, M. A.
SOLID-STATE ELECTRONICS, 2016, 122 : 23 - 31

← 1 2 3 4 5 →