An area-efficient analog VLSI architecture for state-parallel Viterbi decoding

An area-efficient analog VLSI architecture is presented to implement a low-power, state-parallel, rate R = 1/2, constraint length K = 7 Viterbi decoder. A combination of current-mode and switched-capacitor techniques are used in designing the Add-Compare-Select (ACS) module, resulting into a very compact VLSI architecture, implemented in a 64-state hard-decision Viterbi ACS VLSI chip fabricated in a 2 mu m CMOS process through MOSIS. The chip has been tested to operate at 500 kbps data rate and 7.65 mW power dissipation.