Test generation at the algorithm-level for gate-level fault coverage

被引：6

作者：

Bareisa, Eduardas ^{[1
]}

Jusas, Vadus ^{[1
]}

Motiejunas, Kestutis ^{[1
]}

Seinauskas, Rimantas ^{[1
]}

机构：

[1] Kaunas Univ Technol, Software Dept, LT-51390 Kaunas, Lithuania

来源：

MICROELECTRONICS RELIABILITY | 2008年 / 48卷 / 07期

关键词：

D O I：

10.1016/j.microrel.2008.03.017

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a test generation approach that enables to construct functional test patterns at early stages of the design according to the software prototype of the circuit. The presented approach is based on an input-output pin pair and an input-input-output pin triplet fault models. The basic properties of these models are analyzed. Random test generation was implemented on the base of these fault models. ISCAS'85 and ITC'99 benchmark circuits were used for the experiments. The obtained results for the presented fault models were compared with the gate level test generation. The problem of termination of random search is explored and the solution is proposed. (C) 2008 Elsevier Ltd. All rights reserved.

引用

页码：1093 / 1101

页数：9

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