High Performance CNFET-based Ternary Full Adders

被引：23

作者：

Sharifi, Fazel ^{[1
]}

Panahi, Atiyeh ^{[1
]}

Moaiyeri, Mohammad Hossein ^{[1
]}

Sharifi, Hojjat ^{[2
]}

Navi, Keivan ^{[1
]}

机构：

[1] Shahid Beheshti Univ, Comp Sci & Engn Dept, Nanotechnol & Quantum Comp Lab, Tehran, Iran

[2] Vali e Asr Univ Rafsanjan, Dept Comp Engn, Rafsanjan, Iran

来源：

IETE JOURNAL OF RESEARCH | 2018年 / 64卷 / 01期

关键词：

CNFET; Full adder; High speed; Multiple valued logic (MVL); Nanotechnology; Ternary arithmetic circuits; TRANSISTORS INCLUDING NONIDEALITIES; CARBON NANOTUBE ELECTRONICS; COMPACT SPICE MODEL; CIRCUITS; DESIGN; GROWTH; LOGIC; CATALYSTS; EFFICIENT; CHIRALITY;

D O I：

10.1080/03772063.2017.1338973

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature, and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET-based ternary full adders.

引用

页码：108 / 115

页数：8

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