HiSIM-SOTB: A Compact Model for SOI-MOSFET with Ultra-Thin Si-Layer and BOX

被引:0
作者
Miura-Mattausch, M. [1 ]
Feldmann, U. [1 ]
Kikuchihara, H. [1 ]
Nakagawa, T. [2 ]
Ichimiya, H. [1 ]
Miyake, M. [1 ]
Iizuka, T. [1 ]
Mattausch, H. J. [1 ]
机构
[1] Hiroshima Univ, Adv Scienece Matter, Kagamiyama 1-3-1, Higashihiroshima 7398530, Japan
[2] Adv Ind Sci & Technol, Tsukuba, Ibaraki 3058568, Japan
来源
NANOTECHNOLOGY 2012, VOL 2: ELECTRONICS, DEVICES, FABRICATION, MEMS, FLUIDICS AND COMPUTATIONAL | 2012年
关键词
compact model; surface-potential model; Poisson equation; thin body and thin BOX SOI-SMOFET; SILICON;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The SOI-MOSFET has three surfaces, for which electrostatic potential values are very much dependent on applied bias conditions. HiSIM-SOTB has been developed by solving the Poisson equation iteratively to calculate the surface potentails accurately for any bias conditions. It has been verified that the model can indeed reflect structural size variations over a very large range. The model includes all possible charges induced at the three oxide surfaces in the SOI structure. The approach with simultaneous inclusion of the three surface charges can easily make the circuit simulation unstable. To overcome such stability problems we have developed a sophisticated method for reliably solving the Poisson equation. We address the development of solutions to the outlined challenges in our report.
引用
收藏
页码:792 / 795
页数:4
相关论文
共 8 条
[1]   Complete surface-potential-based fully-depleted silicon-on-insulator metal-oxide-semiconductor field-effect-transistor model for circuit simulation [J].
Kitamaru, D ;
Uetsuji, Y ;
Sadachika, N ;
Miura-Mattausch, M .
JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2004, 43 (4B) :2166-2169
[2]  
Kusu S., 2008, IEEE SOI C, P62
[3]   Physical modeling of the reverse-short-channel effect for circuit simulation [J].
Miura-Mattausch, M ;
Suetake, M ;
Mattausch, HJ ;
Kumashiro, S ;
Shigyo, N ;
Odanaka, S ;
Nakayama, N .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2001, 48 (10) :2449-2452
[4]   EXPERIMENTAL 0.25-MU-M-GATE FULLY DEPLETED CMOS/SIMOX PROCESS USING A NEW 2-STEP LOCOS ISOLATION TECHNIQUE [J].
OHNO, T ;
KADO, Y ;
HARADA, M ;
TSUCHIYA, T .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1995, 42 (08) :1481-1486
[5]   Completely surface-potential-based compact model of the-fully depleted SOI-MOSFET including short-channel effects [J].
Sadachika, Norio ;
Kitamaru, Daisuke ;
Uetsuji, Yasuhito ;
Navarro, Dondee ;
Yusoff, Marmee Mohd ;
Ezaki, Tatsuya ;
Mattausch, Hans Juergen ;
Miura-Mattausch, Mitiko .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (09) :2017-2024
[6]  
Sugii N, 2011, IEEE INT SOI CONF
[7]   Controllable inverter delay and suppressing Vth fluctuation technology in Silicon on Thin BOX featuring dual back-gate bias architecture [J].
Tsuchiya, Ryuta ;
Ishigaki, Takashi ;
Morita, Yusuke ;
Yamaoka, Masanao ;
Iwamatsu, Toshiaki ;
Ipposhi, Takashi ;
Oda, Hidekazu ;
Sugii, Nobuyuki ;
Kimura, Shin'ichiro ;
Itoh, Kiyoo ;
Inoue, Yasuo .
2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :475-+
[8]   SCALING THE SI MOSFET - FROM BULK TO SOI TO BULK [J].
YAN, RH ;
OURMAZD, A ;
LEE, KF .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1992, 39 (07) :1704-1710