RETHINKING REFRESH: INCREASING AVAILABILITY AND REDUCING POWER IN DRAM FOR CACHE APPLICATIONS

被引:33
|
作者
Emma, Philip G.
Reohr, William R.
Meterelliyoz, Mesut
机构
关键词
D O I
10.1109/MM.2008.93
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
CACHES USE DATA VERY DIFFERENTLY THAN MAIN MEMORY DOES, SO DRAM CACHES CAN HAVE DRAMATICALLY DIFFERENT REFRESH REQUIREMENTS. MAKING CANONICAL ASSUMPTIONS ABOUT RETENTION TIMES IN DRAM CAN BE DRASTIC OVERKILL WITHIN THE CACHE CONTEXT. USING STANDARD REFRESH RATES MAY BE UNNECESSARY, AND CAN BE A SIGNIFICANT WASTE OF CACHE UTILIZATION AND POWER. IN THIS ARTICLE, WE VIEW "RETENTION TIME'' IN A NEW WAY BY USING STATISTICAL POPULATIONS MORE APPROPRIATE FOR CACHES, AND WE SUGGEST USES OF A CACHE'S INHERENT ERROR-CONTROL MECHANISMS TO REDUCE REFRESH RATES BY SEVERAL ORDERS OF MAGNITUDE.
引用
收藏
页码:47 / 56
页数:10
相关论文
共 50 条
  • [21] Flikker: Saving DRAM Refresh-power through Critical Data Partitionin
    Liu, Song
    Pattabiraman, Karthik
    Moscibroda, Thomas
    Zorn, Benjamin G.
    ACM SIGPLAN NOTICES, 2011, 46 (03) : 213 - 224
  • [22] Reducing Refresh Power in Mobile Devices with Morphable ECC
    Chou, Chiachen
    Nair, Prashant
    Qureshi, Moinuddin K.
    2015 45TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, 2015, : 355 - 366
  • [23] HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips
    Yaglikci, A. Giray
    Olgun, Ataberk
    Patel, Minesh
    Luo, Haocong
    Hassan, Hasan
    Orosa, Lois
    Ergin, Oguz
    Mutlu, Onur
    2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2022, : 815 - 834
  • [24] Reducing DRAM Refresh Rate Using Retention Time Aware Universal Hashing Redundancy Repair
    Choi, Kyu Hyun
    Jun, Jaeyung
    Kim, Minseong
    Kim, Seon Wook
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2019, 24 (05)
  • [25] Unified DRAM and NVM Hybrid Buffer Cache Architecture for Reducing Journaling Overhead
    Zhang, Zhiyong
    Ju, Lei
    Jia, Zhiping
    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 942 - 947
  • [26] Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies
    Agrawal, Aditya
    Jain, Prabhat
    Ansari, Amin
    Torrellas, Losep
    19TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA2013), 2013, : 400 - 411
  • [27] A Low Power DRAM Refresh Control Scheme for 3D Memory Cube
    Wang, Ying
    Han, Yinhe
    Li, Huawei
    2014 IEEE COOL CHIPS XVII, 2014,
  • [28] Reducing practicles while increasing production availability
    Partikeljahl gesenkt und Anlagenver-fügbarkeit erhöht
    Fischer, V.S., 1600, Rek and Thomas Medien AG (46):
  • [29] A Hybrid ECC and Redundancy Technique for Reducing Refresh Power of DRAMs
    Yu, Yun-Chao
    Hou, Chih-Sheng
    Chang, Li-Jung
    Li, Jin-Fu
    Lo, Chih-Yen
    Kwai, Ding-Ming
    Chou, Yung-Fa
    Wu, Cheng-Wen
    2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,
  • [30] P3DC: Reducing DRAM Cache Hit Latency by Hybrid Mappings
    Chi, Ye
    Guo, Ren-Tong
    Liao, Xiao-Fei
    Liu, Hai-Kun
    Yue, Jianhui
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2024, 39 (06) : 1341 - 1360