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- [22] Reducing Refresh Power in Mobile Devices with Morphable ECC 2015 45TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, 2015, : 355 - 366
- [23] HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips 2022 55TH ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE (MICRO), 2022, : 815 - 834
- [25] Unified DRAM and NVM Hybrid Buffer Cache Architecture for Reducing Journaling Overhead PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 942 - 947
- [26] Refrint: Intelligent Refresh to Minimize Power in On-Chip Multiprocessor Cache Hierarchies 19TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH PERFORMANCE COMPUTER ARCHITECTURE (HPCA2013), 2013, : 400 - 411
- [28] Reducing practicles while increasing production availability Fischer, V.S., 1600, Rek and Thomas Medien AG (46):
- [29] A Hybrid ECC and Redundancy Technique for Reducing Refresh Power of DRAMs 2013 IEEE 31ST VLSI TEST SYMPOSIUM (VTS), 2013,