共 50 条
- [1] Timing Window Wiper : A New Scheme for Reducing Refresh Power of DRAM 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), 2017, : 133 - 138
- [2] An approximate DRAM with efficient refresh schemes for low power deep learning applications 2020 INTERNATIONAL CONFERENCE ON ELECTRONICS, INFORMATION, AND COMMUNICATION (ICEIC), 2020,
- [3] Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM Journal of Electronic Testing, 2019, 35 : 485 - 495
- [4] Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2019, 35 (04): : 485 - 495
- [5] Reducing Refresh Overhead with In- DRAM Error Correction Codes 18TH INTERNATIONAL SOC DESIGN CONFERENCE 2021 (ISOCC 2021), 2021, : 211 - 214
- [7] Reducing DRAM Cache Access in Cache Miss via an Effective Predictor PROCEEDINGS OF 2016 IEEE 7TH INTERNATIONAL CONFERENCE ON SOFTWARE ENGINEERING AND SERVICE SCIENCE (ICSESS 2016), 2016, : 501 - 504
- [9] Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction 2018 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2018, : 50 - 51
- [10] DearDRAM: Discard Weak Rows for Reducing DRAM's Refresh Overhead ADVANCED COMPUTER ARCHITECTURE, 2018, 908 : 109 - 124