High SNM 32nm CNFET based 6T SRAM Cell design considering transistor ratio

被引：0

作者：

Dhilleswararao, Pudi ^{[1
]}

Mahapatra, Rajat ^{[1
]}

Srinivas, P. S. T. N. ^{[1
]}

机构：

[1] Natl Inst Technol, Dept Elect & Commun Engn, Durgapur, India

来源：

2014 INTERNATIONAL CONFERENCE ON ELECTRONICS AND COMMUNICATION SYSTEMS (ICECS) | 2014年

关键词：

SRAM; CNFET; SNM; CNT; Cell stability; Cell ratio; Pull up ratio; nanotube diameter; chirality;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Carbon Nanotube Field Effect Transistor (CNFET) is best alternative to design SRAM cell in submicron range because of its excellent electrical properties, high stability, high Performance and low power dissipation in submicron range. This paper proposes a design of 6T SRAM cell based on 32nm CNFET considering nanotube diameter and transistor sizing. By using proper transistor sizing the SRAM cell shows improved performance considering noise margin and power. Compared to the traditional 32nm CMOS based 6T SRAM cell the SRAM cell increases 38% static noise margin (SNM) for read operation, increases 12% static noise margin (SNM) for standby mode operation for same cell ratio and pull up ratio. High SNM is achieved with low nanotube diameter for the SRAM cell.

引用

页数：6