Floating-Body Effect in Partially/Dynamically/Fully Depleted DG/SOI MOSFETs Based on Unified Regional Modeling of Surface and Body Potentials

被引:7
作者
Chiah, Siau Ben [1 ]
Zhou, Xing [1 ]
机构
[1] Nanyang Technol Univ, Novitas, Sch Elect & Elect Engn, Nanoelect Ctr Excellence, Singapore 639798, Singapore
关键词
Compact model (CM); double gate (DG); dynamically depleted (DD); floating body (FB); fully depleted (FD); impact ionization; MOSFET; partially depleted (PD); silicon-on-insulator (SOI); surface potential; unified regional modeling (URM); SUBSTRATE CURRENT MODEL; DEVICES;
D O I
10.1109/TED.2013.2288309
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A compact terminal current/charge model for partially/dynamically/fully depleted (PD)/(DD)/(FD) double-gate (DG) and silicon-on-insulator (SOI) MOSFETs with floating-body (FB) effect based on unified regional modeling of the surface and body potentials is presented. The model accurately describes the physical behavior of the impact-ionization current that gives rise to the hump in the C-V characteristics and the body thickness- and doping-dependent kink effect. The FB potential at the zero-field location in the body is the key to model the electrical characteristics of PD/DD/FD devices with complete body doping and thickness scalability. The model is validated by comparison with I-V and C-V data of the numerical devices in a given range of body doping, body thickness, and temperature. Such a scalable model is important for physical and variability modeling of DG/SOI FinFETs with doped body.
引用
收藏
页码:333 / 341
页数:9
相关论文
共 16 条
[1]  
[Anonymous], 2010, BSIMSOIV4 4 MOSFET M
[2]   Unified substrate current model for MOSFETs [J].
Iniguez, B ;
Fjeldly, TA .
SOLID-STATE ELECTRONICS, 1997, 41 (01) :87-94
[3]   CALCULATION OF THE SPACE CHARGE, ELECTRIC FIELD, AND FREE CARRIER CONCENTRATION AT THE SURFACE OF A SEMICONDUCTOR [J].
KINGSTON, RH ;
NEUSTADTER, SF .
JOURNAL OF APPLIED PHYSICS, 1955, 26 (06) :718-720
[4]   Temperature-dependent kink effect model for partially-depleted SOI NMOS devices [J].
Lin, SC ;
Kuo, JB .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1999, 46 (01) :254-258
[5]  
MIURAMATTAUSCH M, 2010, PROC IEEE INT SOI C, P1, DOI DOI 10.1109/SOI.2010.5641416
[6]  
Miyake M., 2011, P S DRY PROC, P167
[7]   Surface-potential solution for generic undoped MOSFETs with two gates [J].
Shangguan, W. Z. ;
Zhou, Xing ;
Chandrasekaran, Karthik ;
Zhu, Zhaomin ;
Rustagi, Subhash C. ;
Ben Chiah, Sian ;
See, Guan Huei .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (01) :169-172
[8]   A continuous compact MOSFET model for fully- and partially-depleted SOI devices [J].
Sleight, JW ;
Rios, R .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1998, 45 (04) :821-825
[9]   On the-body-source built-in potential lowering of SOI MOSFETs [J].
Su, P ;
Fung, SKH ;
Wyatt, PW ;
Wan, H ;
Niknejad, AM ;
Chan, M ;
Hu, CM .
IEEE ELECTRON DEVICE LETTERS, 2003, 24 (02) :90-92
[10]   Surface-potential-based compact modeling of dynamically depleted SOI MOSFETs [J].
Wu, Weimin ;
Yao, Wei ;
Gildenblat, Gennady .
SOLID-STATE ELECTRONICS, 2010, 54 (05) :595-604