Super self-aligned processing for sub 0.1 μm MOS devices using selective Si1-xGexCVD

Fabrication process was investigated to improve Super Self-aligned ultra-Shallow junction Electrode MOSFET's ((SEMOSFET)-E-3) with a gate length of similar to 0.1 mu m or lower by utilising in-situ impurity-doped Si1-xGex selective epitaxy on the source/drain regions at 550 degrees C by LPCVD. It is found that P- and B-doped Si1-xGex films with the higher Ge fraction have the lower solid solubility of electrically active P and the lower barrier height for W, respectively. Therefore, the higher and the lower Ge fractions of the Si1-xGex film are necessary for n- and p-MOSFET's, respectively, in order to reduce the contact resistivity. A super self-aligned process on the source/drain regions using selective in-situ doped Si1-xGex growth, shallow junction formation, and subsequent very-low-temperature W growth is effective to reduce the source/drain resistance as well as device size.