Integration of CNT in TSV (≤5 μm) for 3D IC Application and Its Process Challenges

被引:0
作者
Ghosh, K. [1 ]
Yap, C. C. [1 ]
Tay, B. K. [1 ]
Tan, C. S. [1 ]
机构
[1] Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
来源
2013 IEEE INTERNATIONAL 3D SYSTEMS INTEGRATION CONFERENCE (3DIC) | 2013年
关键词
Carbon nanotube; Through-silicon via; 3D-IC; Wafer bonding; CARBON NANOTUBE BUNDLES; INTERCONNECTS;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The availability of high density TSVs depends on how smart we miniaturize the interconnect dimension in 3D IC package. A number of considerations include controllable TSV aspect ratio, pitch, and material selection. The International Technology Roadmap for Semiconductors (ITRS) has proposed scaling of TSV diameter down to as low as 2 mu m in the future. However, with TSV scaling, the resistance of the TSV increases significantly. Carbon nanotubes (CNTs) could be a potential alternative material to Cu for VLSI interconnects applications, including TSV, due to their outstanding electrical, mechanical, and thermal properties. Here, we demonstrate a method to integrate carbon nanotubes (CNTs)-filled TSV under 5 mu m diameter that are connected by metal-lines at the bottom and show the facile route of fabrication at low temperature regime. The process challenges are highlighted.
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页数:4
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