Low Power Testable Reversible Combinational Circuits

Testable fault tolerant systems are becoming important for low power electronics circuits. Due to advancement of semiconductor manufacturing technology the requirements for Automatic Test equipment (ATE) has considerably increased. As a result, one of the Design for Testability (DFT) techniques such as Built-In-Self-Test (BIST) is becoming essential part of any high speed low power VLSI design. Conversely, reversible logic is one of the alternative to irreversible logic as there is no loss of bit information from input to output. A low power reversible BIST test pattern generator which provides test vectors to reduce switching activity for minimization of power during testing is proposed in this paper. A gated clock scheme, one of the low power BIST techniques is used to generate the test patterns. The resultant reversible testable circuits can detect any errors that include stuck-at, missing gate, open and short faults for both logical and physical realizations and fault coverage is obtained for these circuits. The power consumption and power-delay product of the designed circuits are found to be reduced in the range of 35 to 90%.