Low-temperature electrical characterization of junctionless transistors

被引：79

作者：

Jeon, Dae-Young ^{[1
,3
]}

Park, So Jeong ^{[1
,3
]}

Mouis, Mireille ^{[1
]}

Barraud, Sylvain ^{[2
]}

Kim, Gyu-Tae ^{[3
]}

Ghibaudo, Gerard ^{[1
]}

机构：

[1] Minatec, Grenoble INP, IMEP LAHC, F-38016 Grenoble, France

[2] CEA LETI Minatec, F-38054 Grenoble, France

[3] Korea Univ, Sch Elect Engn, Seoul 136701, South Korea

来源：

SOLID-STATE ELECTRONICS | 2013年 / 80卷

基金：

新加坡国家研究基金会;

关键词：

Junctionless transistors (JLTs); Scattering mechanisms; Implantation induced defects; Flat-band voltage (V-fb); Threshold voltage (V-th); NANOWIRE TRANSISTORS;

D O I：

10.1016/j.sse.2012.10.018

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility (mu(o)) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage (V-fb), threshold voltage (V-th) and subthreshold swing (S) of JLT devices was also discussed. (C) 2012 Elsevier Ltd. All rights reserved.

引用

页码：135 / 141

页数：7

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