An ultra low-power current-mode sense amplifier for SRAM applications

被引：10

作者：

Kong, ZH

Yeo, KS

Chang, CH

机构：

[1] Nanyang Technol Univ, Sch Elect & Elect Engn, CICS, Singapore 639798, Singapore

[2] Nanyang Technol Univ, Sch Elect & Elect Engn, Div Circuits & Syst, Singapore 639798, Singapore

来源：

JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS | 2005年 / 14卷 / 05期

关键词：

low-power circuit design; static random access memory; current-mode sense amplifier;

D O I：

10.1142/S021812660500274X

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8V/0.18 mu m CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.

引用

页码：939 / 951

页数：13

共 17 条

[1]

Benini L, 2003, ASP-DAC 2003: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, P385

[2] A low power 256 KB SRAM design [J].

Bhaumik, B ;

Pradhan, P ;

Visweswaran, GS ;

Varambally, R ;

Hardi, A .

TWELFTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 1999, :67-70

[3] Conforming block inversion for low power memory [J].

Chang, YS ;

Kyung, CM .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2002, 10 (01) :15-19

[4]

CHANG YS, 1999, IEEE INT C ICCD 99 P, P152

[5] HIGH-SPEED HYBRID CURRENT-MODE SENSE AMPLIFIER FOR CMOS SRAMS [J].

CHEE, PY ;

LIU, PC ;

SIEK, L .

ELECTRONICS LETTERS, 1992, 28 (09) :871-873

[6] Low power VLSI CMOS circuit design [J].

Elmasry, MI .

ICM 2000: PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2000, :4-4

[7]

JAGASIVAMANI M, 2001, IEEE INT S CIRC SYST, V4, P498

[8]

Kang SM, 2003, ISLPED'03: PROCEEDINGS OF THE 2003 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, P205

[9] A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor [J].

Montanaro, J ;

Witek, RT ;

Anne, K ;

Black, AJ ;

Cooper, EM ;

Dobberpuhl, DW ;

Donahue, PM ;

Eno, J ;

Hoeppner, GW ;

Kruckemyer, D ;

Lee, TH ;

Lin, PCM ;

Madden, L ;

Murray, D ;

Pearce, MH ;

Santhanam, S ;

Snyder, KJ ;

Stephany, R ;

Thierauf, SC .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 31 (11) :1703-1714

[10] Special session on low-power Systems on Chips (SOCs) [J].

Piguet, C ;

Renaudin, M ;

Omnès, TJF .

DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS, 2001, :488-494

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