Formal Verification of Signalling Programs with SafeCap

被引：9

作者：

Iliasov, Alexei ^{[1
]}

Taylor, Dominic ^{[2
]}

Laibinis, Linas ^{[3
]}

Romanovsky, Alexander ^{[1
]}

机构：

[1] Newcastle Univ, Newcastle Upon Tyne, Tyne & Wear, England

[2] Systra Scott Lister, London, England

[3] Vilnius Univ, Inst Comp Sci, Vilnius, Lithuania

来源：

COMPUTER SAFETY, RELIABILITY, AND SECURITY (SAFECOMP 2018) | 2018年 / 11093卷

基金：

英国工程与自然科学研究理事会;

关键词：

D O I：

10.1007/978-3-319-99130-6_7

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

SafeCap is a modern toolkit for modelling, simulation and formal verification of railway networks. This paper discusses the use of SafeCap for formal analysis and fully-automated scalable safety verification of solid state interlocking (SSI) programs - a technology at the heart of many railway signalling solutions. The focus of the work is on making it easy for signalling engineers to use the developed technology and thus to help with its smooth industrial deployment. In this paper we explain the formal foundations of the proposed method, its tool support, and their application to real life railway verification problems.

引用

页码：91 / 106

页数：16

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