Design of Power Clamp Circuit with Diode String and Feedback Enhanced Triggering in advanced SOI BCD Process

被引：0

作者：

Tang, Hongju ^{[1
,2
,3
]}

Cai, Xiaowu ^{[1
,2
]}

Liu, Xinghui ^{[3
]}

Liu, Hainan ^{[1
,2
]}

Luo, Jiajun ^{[1
,2
]}

Zhao, Haitao ^{[1
,2
]}

Peng, Rui ^{[1
,2
]}

Xu, Dongsheng ^{[1
,2
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[2] Chinese Acad Sci, Key Lab Silicon Device Technol, Beijing 100029, Peoples R China

[3] Liaoning Univ, Dept Phys, Shenyang 110036, Liaoning, Peoples R China

来源：

2018 14TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2018年

关键词：

Electrostatic discharge (ESD); power clamp circuit; feedback technology; BigFET;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel power clamp circuit is proposed in this paper. By utilizing the feedback technology, BigFET turning on time is increased to 591ns which is 7 times as long as the traditional one. The layout area is efficiently occupied in the novel power clamp circuit which replaces the detective capacitor by a diode string. The proposed circuit has low leakage current and significant ESD performance validated in a 0.181,tm SOI BCD process.

引用

页码：749 / 751

页数：3