A Combination of Evolutionary Algorithm and Mathematical Programming for the 3D Thermal-Aware Floorplanning Problem

被引:0
作者
Cuesta, David [1 ]
Risco-Martin, Jose L. [1 ]
Ayala, Jose L. [1 ]
Ignacio Hidalgo, J. [1 ]
机构
[1] Univ Complutense Madrid, Dept Comp Architecture & Automat, E-28040 Madrid, Spain
来源
GECCO-2011: PROCEEDINGS OF THE 13TH ANNUAL GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE | 2011年
关键词
Multi-Objective Optimization; Evolutionary Computation; Genetic Algorithms; Mathematical Programming; Floorplanning; Thermal Aware Design;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
(1)Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. Additionally, the placement of Through-Silicon-Vias (TSVs) for connecting different layers is one of the key issues in 3D technology. Although a few recent works have considered thermal-aware placement of cores in chip multiprocessor architectures, the concepts of 3D and TSVs have not been conveniently incorporated. Therefore, new suitable exploration methods for the 3D thermal-aware floorplaning problem need to be developed. In this paper we analyze the benefits of two different exploration techniques for the floorplanning problem: Multi-Objective Genetic Algorithm (MOGA) and a Mixed Integer Linear Program (MILP). We present a novel algorithm that uses MILP to minimize average temperature in the 3D chip, whereas uses MOGA to insert TSVs, connecting the layers while the total wire length is minimized. Our experiments with two different 3D chips show that our algorithm achieves 10% reduction in the maximum temperature and thermal gradient.
引用
收藏
页码:1731 / 1738
页数:8
相关论文
共 21 条
[11]  
Govind S., 2009, IEEE 3D SYSTEM INTEG, P1
[12]   Multiobjective microarchitectural floorplanning for 2-D and 3-D ICs [J].
Healy, Michael ;
Vittes, Mario ;
Ekpanyapong, Mongkol ;
Ballapuram, Chinnakrishnan S. ;
Lim, Sung Kyu ;
Lee, Hsien-Hsin S. ;
Loh, Gabriel H. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2007, 26 (01) :38-52
[13]   Thermal-aware floorplanning using genetic algorithms [J].
Hung, WL ;
Xie, Y ;
Vijaykrishnan, N ;
Addo-Quaye, C ;
Theocharides, T ;
Irwin, MJ .
6th International Symposium on Quality Electronic Design, Proceedings, 2005, :634-639
[14]   Developing Structural Dimensions of Service Supply Chain by Analogy with Community Structure [J].
Li, Xiao ;
Gu, Xinjian ;
Liu, Zhenggang .
2009 6TH INTERNATIONAL CONFERENCE ON SERVICE SYSTEMS AND SERVICE MANAGEMENT, VOLS 1 AND 2, 2009, :347-+
[15]  
Loh G., 2010, 3D STACKED MICROPROC, P289
[16]   Exploring temperature-aware design in low-power MPSoCs [J].
Paci, Giacomo ;
Poletti, Francesco ;
Benini, Luca ;
Marchal, Paul .
INTERNATIONAL JOURNAL OF EMBEDDED SYSTEMS, 2007, 3 (1-2) :43-51
[17]   Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs [J].
Pathak, Mohit ;
Lim, Sung Kyu .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (09) :1373-1386
[18]  
Srinivasan J, 2004, 2004 INTERNATIONAL CONFERENCE ON DEPENDABLE SYSTEMS AND NETWORKS, PROCEEDINGS, P177
[19]   A memetic algorithm for VLSI floorplanning [J].
Tang, Maolin ;
Yao, Xin .
IEEE TRANSACTIONS ON SYSTEMS MAN AND CYBERNETICS PART B-CYBERNETICS, 2007, 37 (01) :62-69
[20]   Cell-level placement for improving substrate thermal distribution [J].
Tsai, CH ;
Kang, SM .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2000, 19 (02) :253-266