A Combination of Evolutionary Algorithm and Mathematical Programming for the 3D Thermal-Aware Floorplanning Problem

被引:0
作者
Cuesta, David [1 ]
Risco-Martin, Jose L. [1 ]
Ayala, Jose L. [1 ]
Ignacio Hidalgo, J. [1 ]
机构
[1] Univ Complutense Madrid, Dept Comp Architecture & Automat, E-28040 Madrid, Spain
来源
GECCO-2011: PROCEEDINGS OF THE 13TH ANNUAL GENETIC AND EVOLUTIONARY COMPUTATION CONFERENCE | 2011年
关键词
Multi-Objective Optimization; Evolutionary Computation; Genetic Algorithms; Mathematical Programming; Floorplanning; Thermal Aware Design;
D O I
暂无
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
(1)Heat removal and power density distribution delivery have become two major reliability concerns in 3D stacked technology. Additionally, the placement of Through-Silicon-Vias (TSVs) for connecting different layers is one of the key issues in 3D technology. Although a few recent works have considered thermal-aware placement of cores in chip multiprocessor architectures, the concepts of 3D and TSVs have not been conveniently incorporated. Therefore, new suitable exploration methods for the 3D thermal-aware floorplaning problem need to be developed. In this paper we analyze the benefits of two different exploration techniques for the floorplanning problem: Multi-Objective Genetic Algorithm (MOGA) and a Mixed Integer Linear Program (MILP). We present a novel algorithm that uses MILP to minimize average temperature in the 3D chip, whereas uses MOGA to insert TSVs, connecting the layers while the total wire length is minimized. Our experiments with two different 3D chips show that our algorithm achieves 10% reduction in the maximum temperature and thermal gradient.
引用
收藏
页码:1731 / 1738
页数:8
相关论文
共 21 条
[1]  
[Anonymous], 2009, DESIGN AUTOMATION TE
[2]  
Ayala J.L., 2009, LECT NOTES COMPUTER, V1, P1
[3]   Wire congestion and thermal aware 3D global placement [J].
Balakrishnan, Karthik ;
Nanda, Vidit ;
Easwar, Siddharth ;
Lim, Sung Kyu .
ASP-DAC 2005: PROCEEDINGS OF THE ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2005, :1131-1134
[4]  
Berntsson J, 2004, LECT NOTES COMPUT SC, V3005, P188
[5]  
Chen G., 2003, P ISPD, P75
[6]   A matrix synthesis approach to thermal placement [J].
Chu, CCN ;
Wong, DF .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1998, 17 (11) :1166-1174
[7]   A thermal-driven floorplanning algorithm for 3D ICs [J].
Cong, J ;
Wei, J ;
Zhang, Y .
ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS, 2004, :306-313
[8]   Adaptive Task Migration Policies for Thermal control in MPSoCs [J].
Cuesta, David ;
Ayala, Jose L. ;
Hidalgo, Jose I. ;
Atienza, David ;
Acquaviva, Andrea ;
Macii, Enrico .
IEEE ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2010), 2010, :110-115
[9]   A fast and elitist multiobjective genetic algorithm: NSGA-II [J].
Deb, K ;
Pratap, A ;
Agarwal, S ;
Meyarivan, T .
IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, 2002, 6 (02) :182-197
[10]  
Ekpanyapong M., 2004, TECHNICAL REPORT