Single Event Latch-Up Hardening Using TCAD Simulations in 130 nm and 65 nm Embedded SRAM in Flash-Based FPGAs

In this work 3D-TCAD simulation is used to investigate and harden single event latch-up (SEL) occurring in embedded SRAMs, in both 130 nm and 65 nm Flash-based Field Programmable Gate Arrays (FPGAs). The methodology to perform accurate SEL simulations on realistic designs suitable for high volume manufacturing is presented. One important new finding is that depending on the technology node, the number of SRAM cells included in the 3D structure significantly affects the SEL threshold. The number of SRAM cells needs to be optimized for accurate SEL prediction within a reasonable simulation time. The simulation results are validated using heavy ion and neutron data. After trade-off studies, process mitigation solutions are chosen to improve the SEL threshold in 65 nm and achieve immunity in neutron environment.