Embedded Transitive Closure Network for Runtime Deadlock Detection in Networks-on-Chip

被引:11
作者
Al-Dujaily, Ra'ed [1 ]
Mak, Terrence [1 ]
Xia, Fei [1 ]
Yakovlev, Alexandre [1 ]
Palesi, Maurizio [2 ]
机构
[1] Newcastle Univ, Sch Elect Elect & Comp Engn, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England
[2] Kore Univ, Fac Sci Econ & Sociali, I-94100 Enna, Italy
基金
英国工程与自然科学研究理事会;
关键词
Networks-on-chip; deadlock detection; dynamic programming; transitive closure computation; performance analysis; DESIGN;
D O I
10.1109/TPDS.2011.275
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Interconnection networks with adaptive routing are susceptible to deadlock, which could lead to performance degradation or system failure. Detecting deadlocks at runtime is challenging because of their highly distributed characteristics. In this paper, we present a deadlock detection method that utilizes runtime transitive closure (TC) computation to discover the existence of deadlock-equivalence sets, which imply loops of requests in networks-on-chip (NoCs). This detection scheme guarantees the discovery of all true deadlocks without false alarms in contrast with state-of-the-art approximation and heuristic approaches. A distributed TC-network architecture, which couples with the NoC infrastructure, is also presented to realize the detection mechanism efficiently. Detailed hardware realization architectures and schematics are also discussed. Our results based on a cycle-accurate simulator demonstrate the effectiveness of the proposed method. It drastically outperforms timing-based deadlock detection mechanisms by eliminating false detections and, thus, reducing energy wastage in retransmission for various traffic scenarios including real-world application. We found that timing-based methods may produce two orders of magnitude more deadlock alarms than the TC-network method. Moreover, the implementations presented in this paper demonstrate that the hardware overhead of TC-networks is insignificant.
引用
收藏
页码:1205 / 1215
页数:11
相关论文
共 27 条
  • [1] Al-Dujaily R., 2011, P DES AUT TEST EUR C, P1
  • [2] Anjan K. V., 1995, Proceedings 9th International Parallel Processing Symposium (Cat. No.95TH8052), P537, DOI 10.1109/IPPS.1995.395983
  • [3] Anjan KV, 1996, 10TH INTERNATIONAL PARALLEL PROCESSING SYMPOSIUM - PROCEEDINGS OF IPPS '96, P815, DOI 10.1109/IPPS.1996.508153
  • [4] Ascia G, 2008, IEEE T COMPUT, V57, P809, DOI [10.1109/TC.2008.38, 10.1109/TC.2007.38]
  • [5] Networks on chips: A new SoC paradigm
    Benini, L
    De Micheli, G
    [J]. COMPUTER, 2002, 35 (01) : 70 - +
  • [6] The odd-even turn model for adaptive routing
    Chiu, GM
    [J]. IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2000, 11 (07) : 729 - 738
  • [7] Cormen T., 2001, Introduction to Algorithms
  • [8] Dally W. J., 2004, Principles and Practices of Interconnection Networks
  • [9] DALLY WJ, 1987, IEEE T COMPUT, V36, P547, DOI 10.1109/TC.1987.1676939
  • [10] Duato J., 2004, INTERCONNECTION NETW