ASPICEmodel of p-channel silicon tunneling field-effect transistors for logic applications

In this study, we propose a SPICE model ofp-channel silicon tunneling field-effect transistors (TFETs) for logic applications. To verify our model, electrical characteristics of fabricatedp-TFETs are calibrated by utilizing TCAD and SPICE simulations. We simulate various logic gates, such as complementary TFET (c-TFET) inverters,c-TFET NAND gates, andc-TFET NOR gates using our TFET model. Our simulation shows that ac-TFET inverter can be operated atV(DD)as low as 0.3 V and thatc-TFET logic gates based on our model can operate similar to 1000 times higher frequency than conventional TFET logic gates.