A duty-cycle control circuit with high input-output duty-cycle range

An adjustable duty-cycle control circuit for clock generator systems and high-speed applications is proposed. The designed circuit is based on duty-cycle control circuit but area consumption is reduced by decreasing the control bits from five to four bits and using transistors with minimum size for charge pump circuit. In this new duty-cycle control circuit, the duty-cycle of output clock is adjustable with acceptable duty-cycle range for the input clock from 15% to 60%. If duty-cycle of input clock is 60%, so output duty-cycle will change from 55% to 86% by easily change of the charge and discharge currents of charge pump circuit. The operating frequency is 1 GHz. A 0.18-mu m CMOS technology and 1.8-V supply voltage with 0.5xLSB error in duty-cycle are used to verify the operation of this circuit.