Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage (GIDL) current in 90nm CMOS technology using lightly-doped drain (LDD) NMOSFET. This paper shows that the drain bias V-D has a strong effect on GIDL current as compared with the gate bias V-G at the same drain-gate voltage V-DG. It is found that the difference between I-D in the of state I-D-V-G characteristics and the corresponding one in the off-state I-D-V-D characteristics, which is defined as I-DIFF, versus V-DG shows a peak. The difference between the influences of VD and V-G on GIDL current is shown quantitatively by I-DIFF, especially in 90nm scale. The difference is due to different hole tunnellings. Furthermore, the maximum I-DIFF(I-DIFF,(MAX)) varies linearly with V-DG in logarithmic coordinates and also V-DG at I-DIFF,(MAX) with V-F which is the characteristic voltage of I-DIFF. The relations are studied and some related expressions are given.