An overview on loop tiling techniques for code generation

Loop tiling is a well-known compiler transformation for both sequential and parallel programs optimization. It focuses on the efficient execution of loop nests in order to generate high-performance codes running on modern architectures by increasing the amount of data reuse as well as data locality. Thus, by reordering loop iterations, accesses to the close data become within a relatively short timeframe. Our present work involves a thorough study on the major known tiling techniques. It permits first to uncover several tiling features, e.g. the shape which depends on the target program dependencies, the size where we distinguish between static and parametrized tiling, and the area which aims at tiling for parallelism and/or cache optimization. Then, we present the most recent code generators using the tiling technique in order to highlight the interest of loop tiling transformation for automatic parallelization in general and code generation in particular.