Fully Depleted SOI technologies from digital to RF and beyond

被引：0
作者：
Raskin, Jean-Pierre [1 ]
机构：
[1] Univ Catholique Louvain UCL, Inst Informat & Commun Technol Elect & Appl Math, Pl Levant,2 Stevin Bldg,Bte L5-04-04, B-1348 Louvain La Neuve, Belgium
来源：
2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2018年
关键词：
Silicon-on-Insulator (SOI); Fully Depleted (FD); Radio Frequency (RF); RF and analog performance; self-heating; non-linear behavior; cryogenic temperature; ULTRA-THIN-BODY; CMOS TECHNOLOGY;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication and computing systems will require transistors with better high frequency and high speed performance at lower power consumption. Fully Depleted (FD) SOI technology is foreseen as one of the best candidates and has been intensively studied these last years. Most of the reported data concern its digital performance. In this paper, the analog/RF behavior, self-heating characteristics, non-linear behavior as well as the wideband electrical performance at cryogenic temperature of FD SOI devices are presented.
引用
收藏
页数：3
相关论文
共 10 条
  • [1] Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20nm Low Power CMOS and Beyond
    Andrieu, F.
    Weber, O.
    Mazurier, J.
    Thomas, O.
    Noel, J-P.
    Fenouillet-Beranger, C.
    Mazellier, J-P
    Perreau, P.
    Poiroux, T.
    Morand, Y.
    Morel, T.
    Allegret, S.
    Loup, V.
    Barnola, S.
    Martin, F.
    Damlencourt, J-F
    Servin, I.
    Casse, M.
    Garros, X.
    Rozeau, O.
    Jaud, M-A.
    Cibrario, G.
    Cluzel, J.
    Toffoli, A.
    Allain, F.
    Kies, R.
    Lafond, D.
    Delaye, V.
    Tabone, C.
    Tosti, L.
    Brevard, L.
    Gaud, P.
    Paruchuri, V.
    Bourdelle, K. K.
    Schwarzenbach, W.
    Bonnin, O.
    Nguyen, B-Y
    Doris, B.
    Boeuf, F.
    Skotnicki, T.
    Faynot, O.
    [J]. 2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 57 - +
  • [2] RF SOI CMOS technology on 1st and 2nd generation trap-rich high resistivity SOI wafers
    Esfeh, B. Kazemi
    Makovejev, S.
    Basso, Didier
    Desbonnets, Eric
    Kilchytska, V.
    Flandre, D.
    Raskin, J. -P.
    [J]. SOLID-STATE ELECTRONICS, 2017, 128 : 121 - 128
  • [3] Efficient Multi-VT FDSOI technology with UTBOX for low power circuit design
    Fenouillet-Beranger, C.
    Thomas, O.
    Perreau, P.
    Noel, J-P.
    Bajolet, A.
    Haendler, S.
    Tosti, L.
    Barnola, S.
    Beneyton, R.
    Perrot, C.
    de Buttet, C.
    Abbate, F.
    Baron, F.
    Pernet, B.
    Campidelli, Y.
    Pinzelli, L.
    Gouraud, P.
    Casse, M.
    Borowiak, C.
    Weber, O.
    Andrieu, F.
    Bourdelle, K. K.
    Nguyen, B. Y.
    Boedt, F.
    Denorme, S.
    Boeuf, F.
    Faynot, O.
    Skotnicki, T.
    [J]. 2010 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2010, : 65 - +
  • [4] Hisamoto D, 2000, IEEE T ELECTRON DEV, V47, P2320, DOI 10.1109/16.887014
  • [5] Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit
    Kilchytska, V.
    Arshad, M. K. Md
    Makovejev, S.
    Olsen, S.
    Andrieu, F.
    Poiroux, T.
    Faynot, O.
    Raskin, J. -P.
    Flandre, D.
    [J]. SOLID-STATE ELECTRONICS, 2012, 70 : 50 - 58
  • [6] Liu Q, 2010, S VLSI TECH, P61, DOI 10.1109/VLSIT.2010.5556120
  • [7] Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications
    Makovejev, S.
    Esfeh, B. Kazemi
    Barral, V.
    Planes, N.
    Haond, M.
    Flandre, D.
    Raskin, J. -P.
    Kilchytska, V.
    [J]. SOLID-STATE ELECTRONICS, 2015, 108 : 47 - 52
  • [8] Makovejev Sergej, 2014, Journal of Low Power Electronics and Applications, V4, P201, DOI 10.3390/jlpea4030201
  • [9] Noel J.-P., ESSDERC 2010, P210
  • [10] Planes N., 2012, 2012 IEEE Symposium on VLSI Technology, P133, DOI 10.1109/VLSIT.2012.6242497
1